![]() ![]() Then I saw my first Ryzen WHEA errors in the event log. "bluescreen")ĭid you get a fatal WHEA error? I know that unstable VRAM can cause a fatal WHEA error for "Cache Hierarchy Error", FYI.įor me, running a miner as a research project, to uncover VRAM instability, as it pushed the VRAM the hardest on my Radeon RX 5600 XT, resulted in a large rectangle that was flickering right before Windows 10 20H2 rebooted itself. Just as likely if not more likely unstable VRAM, because it rebooted unexpectedly. There are also internal differences to things like bank group structure, prefetch length and strobe signalling, but these are generally not important unless you're designing a memory chip, and I don't understand these concepts well enough to explain them in detail. I don't understand exactly why, but DDR4 transfers one bit 2 times per internal clock cycle, GDDR5 transfers one bit 4 times per internal clock cycle, GDDR5X and GDDR6 transfer one bit 8 times per internal clock cycle, and GDDR6X transfers two bits 8 times per internal clock cycle. ![]() There is also something that was introduced with GDDR5 which doubled the effective bandwidth, but for some reason no source on the internet seems to know what it is - there's a lot of speculation that it's "quad pumping", but most of the sources I can find say that "quad pumping" is equivalent to QDR, which GDDR5 doesn't support. This is part of what allows GDDR-type memory to have much higher effective bus frequency than normal DDR-type SDRAM, despite running at similar internal clock speeds (~1000-2000MHz). ![]() One difference is that despite retaining the "DDR" part of their name, the latest versions of GDDR (GDDR5X and onwards) are QDR (quad-data-rate), meaning that each pin can transfer data 4 times per internal clock cycle. ![]()
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